1. Technical Field
The present invention relates in general to data processing and, in particular, to improved data processing system and cache memories for data processing systems. Still more particularly, the present invention relates to snoop filtering in a cache memory of a data processing system.
2. Description of the Related Art
A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.
Because multiple processor cores may request write access to a same cache line of data and because modified cache lines are not immediately synchronized with system memory, the cache hierarchies of multiprocessor computer systems typically implement a cache coherency protocol to ensure at least a minimum level of coherence among the various processor core's “views” of the contents of system memory. In particular, cache coherency requires, at a minimum, that after a processing unit accesses a copy of a memory block and subsequently accesses an updated copy of the memory block, the processing unit cannot again access the old copy of the memory block.
A cache coherency protocol typically defines a set of cache coherency states stored in a cache directory in association with the cache lines of each cache hierarchy, as well as a set of coherency messages utilized to communicate the cache state information between cache hierarchies. In a typical implementation, the cache state information takes the form of the well-known MESI (Modified, Exclusive, Shared, Invalid) protocol or a variant thereof, and the coherency messages indicate a protocol-defined coherency state transition in the cache directory of the cache at the requestor and/or the recipients of a memory access request.
The cache directory, which identifies the cache lines contained in the cache and their respective coherency states, is a scarce resource that is accessed by a cache in the servicing of memory access requests by the associated processor core(s) and remote processor cores. Because the cache directory does not scale well with system size and operating frequency, in multiprocessor systems it is sometimes the case that a cache directory is not available to snoop a memory access by a remote processor core, for example, due to one or more competing accesses by a local processor core. In such cases, the cache memory may have to force the operation by the remote processor core to be retried, for example, by providing an appropriate coherency response message. As this scenario is repeated over time in many cache hierarchies throughout the data processing system, memory access requests are subject to higher average latencies, and overall system performance degrades.